I was asked on the TRS-80 Model 1-4 Facebook group about using the internal FPGA memory for ROM emulation. This is a good question.
Splitting the CPU main memory between internal and external access requires a multiplexer on the address and data busses. Not a big deal, but it’s simpler to allocate all of the CPU main memory from one pool. But this is not sufficient reason – if the TRS-80 ROMs were allocated from internal memory, then no external ROM hardware would be needed.
Lets do the math: there is 72k of block memory on Spartan 6 SLX16. Take away 32k for hi res video, 8k for various character generators, and 2k for video character (80×24) leaves 30k.
A Model 1 Level 2 image is 12k, a Model 3 ROM is 14k, model 4 is 8K – we’ve just run out of block RAM.
So, we would be limited to one TRS-80 model per FPGA load. Adding a $1 SPI ROM seems like a good investment to avoid the problem.