PCBWay is amazing. Ordered these board Sunday night – they arrive Thursday!
The FPGA TRS-80 project continues. I have the Z80 core, Model 1 ROM, and 16k of RAM connected. I need to rework the video address generation as there are timing issues.
Below is a capture of the Z80 booting from ROM. Try and find the first few instructions as the CPU disables interrupts and performs a jump instruction.
A deeper dive in the the Digikey parametric search engine reveals that there are 3.3V DIP RAMs and SPI ROMs in DIP packages!
Microchip has the SST25VF080B 8MBit SPI flash in a DIP package which costs a whole $1.07!
I was asked on the TRS-80 Model 1-4 Facebook group about using the internal FPGA memory for ROM emulation. This is a good question.
Splitting the CPU main memory between internal and external access requires a multiplexer on the address and data busses. Not a big deal, but it’s simpler to allocate all of the CPU main memory from one pool. But this is not sufficient reason – if the TRS-80 ROMs were allocated from internal memory, then no external ROM hardware would be needed.
Lets do the math: there is 72k of block memory on Spartan 6 SLX16. Take away 32k for hi res video, 8k for various character generators, and 2k for video character (80×24) leaves 30k.
A Model 1 Level 2 image is 12k, a Model 3 ROM is 14k, model 4 is 8K – we’ve just run out of block RAM.
So, we would be limited to one TRS-80 model per FPGA load. Adding a $1 SPI ROM seems like a good investment to avoid the problem.
The internal memory on an FPGA very fast, dual ported, and quite small. An FPGA that retails for around $30 has about 70kB of block RAM. Retro computer emulations use the internal memory for features that need the performance or can benefit from dual porting, such as full speed access to the video memory with no access flicker.
The main memory of the retro CPU is implemented with external RAM. This external memory is usually high density dynamic memory of 32MB or more in a single chip. It’s a direct descendant of the 4116 and 4164 dynamic RAM chips of the 70’s and 80’s and is very similar to the DDR RAM in a modern PC. Most FPGA development boards come with 32MB or more of external RAM.
Just like the 41xx RAM chips, these memories require periodic refreshing that is synchronized to the accesses for data. This is implemented using FPGA logic, and complicates the design. But the ability to have megabytes of cheap RAM usually makes it worthwhile. Another downside is that the board layout becomes critical because these parts run at high speeds in 20MHz plus range. Consistent trace lengths, special decoupling etc etc.
After a lot of thought, I’ve decided to use a different approach.
I’m going to use 3.3V static RAMs to avoid the refresh and high speed hassles of the DRAMs. I don’t need megabytes of RAM – 256k would be fine. Also, I can’t use the 5V versions because FPGA pins are all 3.3V and level converters triples the parts count.
The 3.3V parts are SMD only, but not ridiculously so.
A surface mount RAM chip
I also need some ROM storage. Using a 3.3V parallel flash ROM just like the RAM is possible, but that adds another big SMD part.
Instead, I’m going to use one or more SPI flash ROMs and have the FPGA copy the appropriate data into RAM when it boots (just like the Model 3 does when using “ROM” BASIC). The SPI ROMs are tiny and cheap and have only 8 pins.
Next step is to do a simple PCB with these parts. There are a few places that will do them at $10 for 10 boards, as long as they are 100mm x 100mm.
Now that the replica of the first computer I ever owned and built is finished (see my 2650 replica), it is time to move on to the first computer I ever used – the TRS-80 Model 1. I spent most of the school Christmas holidays of 1977 in my local Tandy store becoming an expert on this device. Computers have been my career and hobby ever since.
I never actually owned a Model 1 until a few years ago when I acquired two fully operating systems, one with an expansion interface and drives. I’d like a Model 3 and a Model 4, but they are getting hard to find on eBay, and expensive, Besides, I don’t have the room for them all!
There are software emulators for these machines, but that doesn’t fulfill the inner hardware nerd. I want to build something.
There are other TRS-80 replica projects. This guy is building a replica of the Model 1 as close as possible to the original using discrete logic. I like that idea – I recently built the excellent PC-Retro from MTM Scientific. I also found this project with but it has not been updated since 2015.
I’ve decided to build a TRS-80 replica using an FPGA to implement the Z80 core, video generator and most of the I/O and emulation logic, with an Arduino to handle the SD-Card and associated FAT file system. Here is what it will look like:
The intention is to emulate the Model 1, 3 and 4. On-screen menus will be used to select various options. VGA and composite output will be included, and probably HDMI as well. A standard PC keyboard can be used, or a memory-mapped TRS-80 keyboard can be attached. Floppy disks will be emulated by the Arduino, and I’l include a socket for 17xx/27xx controller chip as well.
I’ve got the basic video timing working with a Xilinx Spartan 3 FPGA (see below) and the next step is include the Z80 core and a ROM image. Eagle eyed readers will see slight artifacts on the bottom of the second row of graphics characters – they will be fixed!
I’m open to suggestions and comments. Please email to firstname.lastname@example.org or the various Facebook groups dedicated to the TRS-80 and DIY Z-80
The problem with PIPBUG has been found, and the problem was nothing to do with PIPBUG!
The first 18up5 board that I built has always worked without issues, but the second “pretty” board did not. It took an embarrassingly long time to notice that the second board was missing the interrupt jumpers JP2 and JP3, and that these were also missing from the instructions.
Once these were installed, everything workied again!
If you are having problems with the G command not working, then make sure you have these jumpers installed. These prevent the CPU from getting an immediate (and unhandled) interrupt whenever a user program is executed.
There is a problem with the modified PIPBUG EPROM that was originally provided for use at 300/4800 baud. It *mostly* worked, but the “G” command was broken.
I’ve uploaded new copies of a PIPBug image from an original 2608 device, but I’ve not yet been able to create or test a new 300/4800 baud version as my EPROM burner is broken.
When I can, I will upload new versions to the git repo at:
The 18up5 board has been tested, and is working as expected. PIPBUG is running at 4800 board, which is a pleasant increase over the original 110.